In connection with MIS (Metal Insulator Semiconductor) field effect transistors (MISFETs), the reduction in size has lead to simultaneous improvement of integration and performance. Also for SRAMs that use MISFETs, miniaturized MISFETs have contributed to increasing capacity. In recent years, SRAMs have reached the level that a gate insulating film has a thickness of at most 2 nm and a gate length of at most 50 nm.
However, at this level, simple further miniaturization may disadvantageously lead to an increase in leakage current or in a variation in characteristics. Thus, further miniaturization is now difficult. Hence, the related technique that uses planar MISFETs has difficulty further increasing the integration degree of SRAMs.
In recent years, various techniques that utilize vertical MISFETs in order to improve the integration degree are disclosed in, for example, JP06-069441A, JP07-099311A, JP08-088328A, JP09-232447A, JP10-079482A, and JP2003-224211A.
The vertical MISFET is configured such that a channel current flows perpendicularly to a substrate surface (up-down direction), whereas in the planar MISFETs, a channel current flows horizontally with respect to the substrate surface. Compared to the use of the planar MISFET, the use of the vertical MISFET with the structure described above enables the reduction in the occupied area on the substrate.